1. Field of the Invention
The present invention relates to an asynchronous bus interface circuit, and, more particularly, to an asynchronous bus interface circuit arranged between an asynchronous bus and a macro circuit in a microcomputer.
2. Description of the Related Art
Some microcomputers, for being embedded into various devices and controlling the devices, have the structure wherein an asynchronous bus connects a CPU performing operations and various macro circuits for controlling a target device. Each of the macro devices equips one of function blocks, such as an input/output control of the target device, into which various functions for controlling the target device are arranged. In recent years, in such an embedded microcomputer, the operational clock frequency of a macro circuit tends to be lowered so that the power consumption of the microcomputer can be decreased. If the operational clock frequency of the macro circuit is lowered, the conventional embedded microcomputer fails into a bus-wait state for a long time when the CPU transmits data to the macro circuit. Such a long bus-wait causes a lowering of the processing performance.
As a technique for overcoming the above problem, there is a embedded microcomputer comprising a CPU, an synchronous bus, a macro device and an asynchronous bus interface circuit arranged between the asynchronous bus and the macro circuit described below. The asynchronous bus interface circuit performs handshaking with a CPU through an asynchronous bus so as to store temporarily the received data from the CPU, output the temporarily stored data to the macro circuits in synchronization with an operational clock of the macro circuit. FIG. 6 is a block diagram showing the exemplary structure of such a microcomputer. As illustrated in FIG. 6, this microcomputer includes a CPU 51, an asynchronous bus 52, a plurality of macro circuits 53 and a plurality of asynchronous bus interface circuits 54. The CPU 51 is connects directly to the asynchronous bus 52, and each of the macro circuits 53 is connected to the asynchronous bus 52 respectively through the asynchronous bus interface circuits 54.
The asynchronous bus interface circuits 54 can input and output data to and from the asynchronous bus 52 and the respective macro circuits 53. The asynchronous bus interface circuits 54 receive an internal clock signal 60 respectively from the macro circuits 53. Each of the asynchronous bus interface circuits 54 includes an external register 55, an internal register 57 and an arbitration circuit 58. The external register 55 outputs data written thereinto from the CPU 51 through the asynchronous bus 52, to the internal register 57 in synchronization with the internal clock signal 60. The data output from the external register 55 is written into the internal register 57 in response to an internal register-write signal 59 to be output from the arbitration circuit 58. The internal register 57 outputs the written data to one of the macro circuits 53 in synchronization with the internal clock signal 60.
The arbitration circuit 58 includes, as illustrated in FIG. 7, an effective-data-signal generation circuit 61 and an internal register-write-signal generation circuit 62 both of which operate in synchronization with the internal clock signal 60. Upon reception of an external register-write signal 63 output from the CPU 51 through the asynchronous bus 52, the effective-data-signal generation circuit 61 generates an external register-data request signal 65 in a disable state and an effective data signal 64. Then, the effective-data-signal generation circuit 61 outputs the effective data signal 64 and the external register-data request signal 65, respectively to the internal register-write-signal generation circuit 62 and the asynchronous bus 52. The CPU 51 receives the external register-data request signal 65 in a disable state through the asynchronous bus 52.
The effective data signal 64 and the external register-data request signal 65 are kept thereinto until data written into the external register 55 is for written into the internal register 57. Upon reception of the effective data signal 64, the internal register-write signal generation circuit 62 generates the internal register-write signal 59, and outputs the generated signal 59 to the internal register 57. In the structure where such an asynchronous bus interface circuit 54 is included in each of the microcomputers, the CPU 51 can output data regardless of the operational clock frequency of the macro circuits 53.
It should be mentioned, however, that it is forbidden to write new data into the external register while transmitting data from the external register to the internal register in each asynchronous bus interface circuit, in the above-described conventional microcomputer. Hence, in the case where data is written into the same macro circuit over and over, the CPU falls into a bus wait state, and hence lowering the processing performance of the microcomputer.
In the case where the conditions of a target device to be controlled dramatically change, it is necessary that the microcomputer always write new data to the macro circuit in accordance with the change in the conditions. Accordingly, a plurality of write requests for writing data to a single external register from the CPU may be transmitted. In this case, it is forbidden to write the latest data into the external register when intended to do so, the latest data necessary for controlling the target device can not be input to the macro circuit.